1. general description the 74aup1t34-q100 provides a single buffer with two separate supply voltages. input a is designed to track v cc(a) . output y is designed to track v cc(y) . both, v cc(a) and v cc(y) accepts any supply voltage from 1.1 v to 3.6 v. this feature allows universal low voltage interfacing between any of the 1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v voltage nodes. schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire v cc range from 1.1 v to 3.6 v. this device ensures a very low static and dynamic power consumption across the entire v cc range from 1.1 v to 3.6 v. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventin g the damaging backflow current through the device when it is powered down. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 1.1 v to 3.6 v ? high noise immunity ? complies with jedec standards: ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8-b (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 class 3a. exceeds 5000 v ? hbm jesd22-a114f class 3a. exceeds 5000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? wide supply voltage range: ? v cc(a) : 1.1 v to 3.6 v ? v cc(y) : 1.1 v to 3.6 v ? low static power consumption; i cc = 0.9 ? a (maximum) ? each port operates over the full 1.1 v to 3.6 v power supply range ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 3.6 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation 74aup1t34-q100 low-power dual supply translating buffer rev. 1 ? 5 june 2013 product data sheet
74aup1t34_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 5 june 2013 2 of 18 nxp semiconductors 74aup1t34-q100 low-power dual supply translating buffer 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning table 1. ordering information type number package temperature range name description version 74AUP1T34GW-Q100 ? 40 ? c to +125 ? c tssop5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm sot353-1 table 2. marking type number marking code [1] 74AUP1T34GW-Q100 pq fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram 001aac538 2a 4 y 001aac537 24 001aac536 y a fig 4. pin configuration sot353-1 $ 8 3 7 4 9 & |